| Name | Version | Summary | date |
| peakrdl-regblock |
0.22.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-04-01 05:27:07 |
| peakrdl-ipxact |
3.4.4 |
Import and export IP-XACT XML to/from the systemrdl-compiler register model |
2024-03-30 06:04:08 |
| systemrdl-compiler |
1.27.3 |
Parse and elaborate front-end for SystemRDL 2.0 |
2024-01-12 06:12:39 |
| speedy-antlr-tool |
1.4.3 |
Generate an accelerator extension that makes your Antlr parser in Python super-fast! |
2023-10-29 03:38:20 |
| peakrdl |
1.1.0 |
Command-line tool for control/status register automation and code generation. |
2023-10-26 04:34:44 |
| peakrdl-html |
2.10.1 |
HTML documentation generator for SystemRDL-based register models |
2023-06-02 06:19:23 |
| peakrdl-systemrdl |
0.3.0 |
Write a register model to a SystemRDL file |
2023-04-12 04:34:58 |
| git-me-the-url |
2.1.0 |
Generate sharable links to your Git source |
2023-03-13 00:42:30 |
Alex Mykyta